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Memory barrier
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#	Item
121	Mathematizing C++ Concurrency Mark Batty Scott Owens Susmit Sarkar Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2010-12-10 02:43:43 Computer memory Concurrency control Concurrency Compiler construction Transaction processing Java Memory Model Memory barrier Memory ordering Lock Computing Computer architecture Software engineering
122	Fences in Weak Memory Models Jade Alglave1 , Luc Maranget1 , Susmit Sarkar2 , and Peter Sewell2 1 INRIA Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2010-07-16 08:12:44 Computer memory Memory barrier Parallel computing
123	Understanding POWER Multiprocessors Susmit Sarkar1 1 Peter Sewell1 Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2011-10-26 17:19:12 Computer memory Central processing unit Parallel computing Threads Memory barrier Memory model Data dependency Register renaming Microarchitecture Computing Computer architecture Concurrent computing
124	Relaxed memory models must be rigorous ˇ c´ık3 Susmit Sarkar2 Francesco Zappa Nardelli1 Peter Sewell2 Jaroslav Sevˇ Luc Maranget1 Mark Batty2 Jade Alglave1 1 Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2009-07-13 08:43:45 X86 architecture Computer memory X86-64 X86 Java Memory Model Memory barrier Spinlock Low-level programming language MOV Computer architecture Computing Instruction set architectures
125	A better x86 memory model: x86-TSO (extended version) Scott Owens Susmit Sarkar Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2009-03-25 12:38:18 X86 architecture X86 instructions Machine code Central processing unit X86 MOV Memory ordering Memory barrier Assembly language Computer architecture Computing Computer memory
126	A CompCertTSO: A Verified Compiler for Relaxed-Memory Concurrency ˇ C ˇ ´IK, Microsoft JAROSLAV SEV VIKTOR VAFEIADIS, MPI-SWS Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2013-05-16 11:01:24 Compiler construction Logic in computer science Programming language implementation Formal methods Memory barrier Java Memory Model Memory model Thread-local storage Compiler optimization Computing Software engineering Computer memory
127	Noname manuscript No. (will be inserted by the editor) Fences in Weak Memory Models (Extended Version) Jade Alglave1,3 · Luc Maranget1 · Susmit Sarkar2 · Peter Sewell2 Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2012-10-31 12:22:04 Computing Dependence analysis Parallel computing Function Computer memory Mathematics Memory barrier
128	A Tutorial Introduction to the ARM and POWER Relaxed Memory Models Luc Maranget INRIA Susmit Sarkar University of Cambridge Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2012-10-10 05:25:03 Computer memory Concurrency control Microprocessors Compiler construction Memory barrier Thread Linearizability Lock Microarchitecture Computing Computer architecture Computer hardware
129	The Semantics of Power and ARM Multiprocessor Machine Code Jade Alglave2 Anthony Fox1 Samin Ishtiaq3 Magnus O. Myreen1 Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2008-11-14 13:08:57 Central processing unit Computer memory Concurrency control Parallel computing Memory barrier Load-link/store-conditional ARM architecture Instruction set ALGOL 68 Computer architecture Computing Computer hardware
130	Final version of CACM Research Highlights paper, May 17, 2010 x86-TSO: A Rigorous and Usable Programmer’s Model for x86 Multiprocessors Peter Sewell Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2010-05-17 05:29:00 X86 instructions Computer memory Machine code Assembly languages Spinlock X86 assembly language X86 MOV Memory barrier Computer architecture Computing X86 architecture

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